The present invention relates generally to integrated circuits, and more specifically to the storage of data in integrated circuits.
Computer systems, video games, electronic appliances, digital cameras, and myriad other electronic devices include memory for storing data related to the use and operation of the device. A variety of different memory types are utilized in these devices, such as read only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory (FLASH), and mass storage such as hard disks and CD-ROM or CD-RW drives. Each memory type has characteristics that better suit that type to particular applications. For example, DRAM is slower than SRAM but is nonetheless utilized as system memory in most computer systems because DRAM is inexpensive and provides high density storage, thus allowing large amounts of data to be stored relatively cheaply. A memory characteristic that often times determines whether a given type of memory is suitable for a given application is the volatile nature of the storage. Both DRAM and SRAM are volatile forms of data storage, which means the memories require power to retain the stored data. In contrast, mass storage devices such as hard disks and CD drives are nonvolatile storage devices, meaning the devices retain data even when power is removed.
Current mass storage devices are relatively inexpensive and high density, providing reliable long term data storage at relatively cheap. Such mass storage devices are, however, physically large and contain numerous moving parts, which reduces the reliability of the devices. Moreover, existing mass storage devices are relatively slow, which slows the operation of the computer system or other electronic device containing the mass storage device. As a result, other technologies are being developed to provide long term nonvolatile data storage, and, ideally, such technologies would also be fast and cheap enough for use in system memory as well. The use of FLASH, which provides nonvolatile storage, is increasing popular in many electronic devices such as digital cameras. While FLASH provides nonvolatile storage, FLASH is too slow for use as system memory and the use of FLASH for mass storage is impractical, due in part to the duration for which the FLASH can reliably store data as well as limits on the number of times data can be written to and read from FLASH.
Due to the nature of existing memory technologies, new technologies are being developed to provide high density, high speed, long term nonvolatile data storage. One such technology that offers promise for both long term mass storage and system memory applications is Magneto-Resistive or Magnetic Random Access Memory (MRAM). FIG. 1A is a functional diagram showing a portion of a conventional MRAM array 100 including a plurality of memory cells 102 arranged in rows and columns. Each memory cell 102 is illustrated functionally as a resistor since the memory cell has either a first or a second resistance depending on a magnetic dipole orientation of the cell, as will be explained in more detail below. Each memory cell 102 in a respective row is coupled to a corresponding word line WL, and each memory cell in a respective column is coupled to a corresponding bit line BL. In FIG. 1A, the word lines are designated WL1-3 and the bit lines designated BL1-4, and may hereafter be referred to using either these specific designations or generally as word lines WL and bit lines BL. Each of the memory cells 102 stores information magnetically in the form of an orientation of a magnetic dipole of a material forming the memory cell, with a first orientation of the magnetic dipole corresponding to a logic xe2x80x9c1xe2x80x9d and a second orientation of the magnetic dipole corresponding to a logic xe2x80x9c0.xe2x80x9d The orientation of the magnetic dipole of each memory cell 102, in turn, determines a resistance of the cell. Accordingly, each memory cell 102 has a first resistance when the magnetic dipole has the first orientation and a second resistance when the magnetic dipole has the second orientation. By sensing the resistance of each memory cell 102, the orientation of the magnetic dipole and thereby the logic state of the data stored in the memory cell 102 can be determined.
FIG. 1B is a partial cross-sectional isometric view of the portion of the MRAM array 100 of FIG. 1A illustrating in more detail the position of each memory cell 102 relative to the corresponding word line WL and bit line BL. Each memory cell 102 is sandwiched between the corresponding word line WL and bit line BL. To write data to a particular memory cell 102, a row current IROW is applied to the word line WL coupled to cell and a column current ICOL is applied to the bit line BL coupled to the cell. In the following description, the memory cell 102 being written to or programmed is termed the xe2x80x9cselectedxe2x80x9d memory cell, and the word line WL and bit line BL coupled to the selected memory cell are termed the selected word line and selected bit line, respectively, with all other word lines and bit lines being unselected lines. In the MRAM array 100, the word lines WL are positioned parallel to an X-axis and the bit lines BL positioned parallel to an orthogonal Y-axis. Accordingly, the row current IROW flows in the X direction and generates a corresponding magnetic field BY in the Y direction, with the magnetic field BY being applied to the selected memory cell 102 along with every other memory cell in the row. Similarly, the column current ICOL flows in the Y direction and generates a corresponding magnetic field BX in the X direction, with the magnetic field BX being applied to the selected memory cell 102 along with every other memory cell in the column. Although the magnetic fields BY, BX are described herein as being in the Y and X directions, respectively, one skilled in the art will understand that the magnetic field BY is a transverse field relative to the X-axis and has components in the YZ plane, where Z is an axis orthogonal to the X and Y axes, and that the magnetic field BX is similarly a transverse field relative to the Y axis and has components in the XZ plane.
Only the selected memory cell 102 is subjected to both the magnetic field BY generated by the row current IROW and the magnetic field BX generated by the column current ICOL. FIG. 1C is a cross-sectional isometric view illustrating the selected memory cell 102 in more detail. The magnetic fields BX, BY applied to the selected memory cell 102 combine to form a magnetic field having a sufficient magnitude and orientation to change the magnetic dipole orientation of the memory cell 102 and in this way write data into the selected memory cell. When the row current IROW and column current ICOL are applied in first directions, the magnetic dipole of the selected memory cell 102 is oriented in a first direction in response to the resulting magnetic fields BX, BY, and when the row and column currents are applied in the opposite directions, the magnetic dipole of the cell is oriented in a second direction in response to the applied magnetic fields. In this way, the row and column currents IROW, ICOL determine the magnetic dipole orientation of the selected memory cell 102 which, in turn, determines the resistance of the cell to thereby store a bit of information in the cell, with the bit being either a 0 or a 1 depending on the resistance of the cell.
FIG. 1D is a cross-sectional view illustrating in more detail the magnetic fields BX, BY applied to the selected memory cell 102 coupled to bit line BL3 and adjacent memory cells coupled to bit lines BL2, BL4. Ideally, the magnetic field BX is applied only to the selected memory cell 102 coupled to bit line BL3 as illustrated by the flux line 104. The actual magnetic field BX, however, is applied not only to the selected memory cell 102 but also to the adjacent memory cells coupled to bit lines BL2, BL4 as illustrated by the flux line 106. As previously mentioned, the row and column currents IROW, ICOL must have sufficient magnitudes to change the magnetic dipole orientation of the selected memory cell 102 coupled to bit line BL3. An increase in the magnitude of the column current ICOL results in a corresponding increase in the magnitude of the generated magnetic field BX, which is applied not only to the selected memory cell 102 coupled to bit line BL3 but also to adjacent memory cells 102 coupled to bit lines BL2, BL4. As the magnitude of the column current ICOL is increased to ensure the selected memory cell 102 is reliably written to or programmed, the increased magnitude of the resulting magnetic field BX can result in the adjacent memory cells coupled to bit lines BL2, BL4 also being programmed. This could undesirably change the data stored in the adjacent memory cells 102 coupled to bit lines BL3. Thus, in the conventional MRAM array 100 the ability to increase the column current ICOL to reliably write data to a selected memory cell 102 is limited due to the unwanted result of potentially writing data to unselected adjacent memory cells. This limit on the magnitude of the column current ICOL can adversely affect performance of the MRAM array 100. For example, where the magnitude of the column current ICOL is less than a desired value to reduce the possibility of programming adjacent memory cells 102, the selected memory cell may need to be written to multiple times to ensure the cell stores the proper data. Moreover, the time the selected memory cell 102 must be exposed to the resulting magnetic field BX may increase, undesirably increasing the time it takes to write data to the memory cells and thereby slowing overall operation of the MRAM array 100.
There is a need for applying currents having sufficient magnitudes to reliably program MRAM memory cells while not affecting the data stored in memory cells proximate the selected memory cells. While the above discussion relates to MRAMs, the concepts may also be applied to other memory technologies where electromagnetic fields are applied to memory cells to store data in the cells.
An MRAM array includes a plurality of memory cells arranged in rows and columns are programmed, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line. According to one aspect of the present invention, a method for writing data to selected memory cells includes applying a row current to a selected word line and applying a first column current to a selected bit line. The column current is applied in a first direction. Second column currents are applied to at least the unselected bit lines adjacent the selected bit line. The second column currents are applied in a second direction that is opposite the first direction.